Analog-to-digital converters (“ADCs”) convert an incoming analog signal to a corresponding series of digital bits. Image sensing devices (i.e., image sensors) generate analog signals that are typically converted by ADCs to digital bit values as part of image processing. Image sensors typically employ light detecting elements (e.g., photosensors) and are used in various applications. Such image sensors may be formed using a variety of fabrication techniques. Currently, two commonly fabricated image sensors are CMOS image sensors and charge coupled device (CCD) image sensors. Each sensor generally includes an array of pixels containing the photosensors. The image sensors typically use photosensors in the form of photogates, phototransistors or photodiodes.
When an image is focused on the image sensor array (also called an “imager array” or “pixel array”), light corresponding to the image is directed to the pixels usually through micro-lenses. Each micro-lens may be used to direct incoming light through a circuitry region of the corresponding pixel to the photosensor region, thereby increasing the amount of light reaching the photosensor. It is known in the art to use circuitry that includes storage regions (for example, floating diffusion regions) that collect pixel charge representing the light reaching the photosensors.
In a CMOS imager, the pixel array discharges this pixel charge as an analog voltage signal that is proportional to the light collected by the photosensor. It is known in the art to use row select transistors to select a particular row in the pixel array and cause the storage element (e.g., a floating diffusion region) for each pixel in the selected row to discharge its voltage for further processing by image sensor circuitry. In this way, the pixel array circuitry discharges the voltage stored in each column of the pixel array one row (i.e., the selected row) at a time. The discharged analog voltage signals may be used to replicate an image represented by the light incident on the photosensors of the array (i.e., the incident light). For example, the discharged analog voltage signals may be used to display a corresponding image on a monitor or to otherwise provide information about the image.
It is known in the art to convert analog voltage signals to digital signals using an ADC that uses a successive approximation (“SAR”) method, where digital bit values are successively approximated using the values of previously generated bits. An ADC typically includes: a sample and hold circuit for sampling and holding analog signals; a comparator for comparing an input analog signal to a feedback analog signal and for outputting a corresponding digital value; memory for storing digital bit values; and a feedback loop comprising a digital-to-analog converter (“DAC”) for generating the feedback analog signal. In operation, the DAC receives a digital value (e.g., a digital bit previously generated by the ADC) and outputs a corresponding analog signal that is applied to one of the comparator inputs and used to generate the next successive digital bit value of the digital bit series.
Error signals may, arise in the analog voltage signal applied to the comparator of an ADC employed in an image sensor. For example, such errors may arise because of floating diffusion reset noise embedded in the incoming analog voltage signal. In image sensors, the floating diffusion region of a pixel acts as a capacitor that stores charge corresponding to the light incident on the pixel photosensors. Each time pixel charge is read out of the floating diffusion region, the floating diffusion region must be set to a reference level (the “floating diffusion reset level”) in order to accept the next incoming charge. Thus, when the floating diffusion region of the pixel array discharges, the resulting output (e.g., Vsig) includes not only the charge representing the incident light, but may also include noise in the floating diffusion reset level. Such noise is undesirable.
For a comparator in the form of an operational amplifier, error signals also may arise due to offset values that are inherent to the operational amplifier and therefore embedded in the operational amplifier output. Such offset values are undesirable.
Successive approximation type ADCs that require one storage capacitor for storing the value of each bit of an N-bit series (i.e., N capacitors) are known in the art. For example, if ten bits are to be converted, the ADC circuitry includes ten capacitors. Such configurations require significant die area to accommodate the numerous circuit elements. Moreover, for high resolution ADCs, the size of the capacitors significantly increases from least significant bit (“LSB”) to most significant bit (“MSB”) in order to compensate for charge leakage and thermal noise on the MSB capacitor. For example, SARs with charge-sharing DACs are known where each of the N capacitors are sized 20, 21, 22, 24 . . . 2N relative to one another. Such SARs rely on capacitor matching and a large ratio from the largest capacitance to the smallest.
Other DACs having a limited number of capacitors (e.g., two) are known in the art. However, the comparator of these SAR ADCs typically process signals MSB first, LSB last, while serial DACs typically process bits LSB first, MSB last. In order to use such a DAC in an ADC, the comparator of the ADC must completely convert the analog input to digital values before the LSB is generated and DAC processing can begin. This is undesirable.
Furthermore, these known SAR ADCs fail to compensate for offset errors prior to conversion of the pixel cell output (the analog signals) used to generate the digital bits. Therefore these known SAR ADCs fail to adequately account for offset errors from either the comparator or the pixel cells which is undesirable.
DACs that process MSB first, LSB last are also known, but these DACs typically require integrator circuitry prior to transferring the analog output to a comparator. Such integrator circuitry requires additional electronic components (e.g., a separate operational amplifier and a capacitor network and takes up additional die space), and is therefore undesirable.
Other DACs that process MSB first, LSB last are limited to use in monotonic DACs (i.e., the DACs' output either increases (for a digital input of 1) or stays the same (for an input of 0)). Thus, the DAC output is not sufficiently sensitive for high resolution applications such as high speed image sensor applications.
Accordingly, there is a desire and need for an image sensor having a successive approximation type analog-to-digital converter comprising circuitry that includes a minimal number of circuit components that take up minimal die area.
There is also a need for an improved method of processing signals through an image sensor using a successive approximation type analog-to-digital conversion method having a serial digital-to-analog converter that is capable of processing bits MSB first, LSB last.
There is further a need for an improved method of correcting for error signals in a successive approximation type analog-to-digital converter.
Further there is a need for an improved method of converting analog signals to digital signals using a successive approximation type analog-to-digital converter comprising a digital to analog conversion method for high resolution applications.